An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation-Reference-Cited by-同舟云学术

An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation

Published:2022-06 Issue:6 Volume:57 Page:1765-1775
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

He Yuming¹^ORCID,van den Heuvel Johan¹,Mateman Paul¹,Allebes Erwin¹^ORCID,Traferro Stefano¹,Dijkhuis Johan¹,Bunsen Keigo²^ORCID,Vis Peter¹,Breeschoten Arjan¹,Liu Yao-Hong¹^ORCID,Matsumoto Tomohiro²,Bachmann Christian¹

Affiliation:

1. imec, Eindhoven, AE, The Netherlands

2. Sony Semiconductor Solutions Corporation, Atsugi, Japan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9781662/09737302.pdf?arnumber=9737302

Reference31 articles.

1. A 365fsrms-jitter and ?63 dBc-fractional spur 5.3 GHz-ring-DCO-based fractional-N DPLL using a DTC second/third- order nonlinearity cancelation and a probability-density-shaping ??M;park;IEEE ISSCC Dig Tech Papers,0

2. A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS

3. A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

4. A 0.2–1.45-GHz Subsampling Fractional- $N$ Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection

5. A 1.33 mW, 1.6psrms-Integrated-Jitter, 1.8-2.7 GHz Ring-Oscillator-Based Fractional-N Injection-Locked DPLL for Internet-of-Things Applications

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning;Electronics;2024-07-05

2. A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance;Microelectronics Journal;2024-01

4. An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

5. Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration;IEEE Journal of Solid-State Circuits;2024-01