A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration-Reference-Cited by-同舟云学术

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A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Published:2014-01 Issue:1 Volume:49 Page:50-60
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Musa Ahmed,Deng Wei,Siriburanon Teerachot,Miyahara Masaya,Okada Kenichi,Matsuzawa Akira

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6690141/06644316.pdf?arnumber=6644316

Cited by 73 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Synthesizable Digital Frequency-Locked Loop Widely Tunable up to 640 MHz in 130 nm CMOS;2024 11th International Conference on Electrical, Electronic and Computing Engineering (IcETRAN);2024-06-03

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4. An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

5. Voltage controlled oscillator with active inductive and capacitive tuning;International Journal of Information Technology;2023-12-25

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