17.5 A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor
Author:
Affiliation:
1. Tsinghua University,Beijing,China
Funder
NSFC
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067475.pdf?arnumber=10067475
Reference6 articles.
1. A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp;zhan;ISSCC,2022
2. A 1 MS/s to 1 GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm;hershberg;IEEE Symp VLSI Circuits,2020
3. 28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
4. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
5. 3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier
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1. A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS;Microelectronics Journal;2024-04
2. A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04
3. 9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
4. 9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
5. 9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
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