9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm-Reference-Cited by-同舟云学术

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9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm

Published:2024-02-18 Issue: Volume: Page:170-172
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Lim Yong¹,Lee Jaehoon¹,Lee Jongmi¹,Lim Kwangmin¹,Oh Seunghyun¹,Lee Jongwoo¹,Kwak Sung-Ung¹

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454422.pdf?arnumber=10454422

Reference11 articles.

1. 11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers

2. A 1mW 71.5dB SNDR 50MS/s 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC;Lim

3. A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS

4. 3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion

5. A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm

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