11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers-Reference-Cited by-同舟云学术

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11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers

Published:2014-02 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
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Author:

Lim Yong,Flynn Michael P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6747109/6757318/06757400.pdf?arnumber=6757400

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

2. A 2.5-Vpp PVT-insensitive high dynamic range output stage using bulk voltages adjustment;IEICE Electronics Express;2022-06-10

3. A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

4. A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS;Electronics;2021-12-20

5. A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector;Analog Integrated Circuits and Signal Processing;2021-03-09

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