A 2.5-Vpp PVT-insensitive high dynamic range output stage using bulk voltages adjustment-Reference-Cited by-同舟云学术

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A 2.5-Vpp PVT-insensitive high dynamic range output stage using bulk voltages adjustment

Published:2022-06-10 Issue:11 Volume:19 Page:20220180-20220180
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Liu Xiangcheng¹,Chen Yingyu¹,Tang Zhangwen¹

Affiliation:

1. State Key Lab of ASIC & System, Fudan University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/19/11/19_19.20220180/_pdf

Reference30 articles.

1. [1] B. Hershberg, et al.: “Ring amplifiers for switched capacitor circuits,” IEEE J. Solid-State Circuits 47 (2012) 2928 (DOI: 10.1109/jssc.2012.2217865).

2. [2] J. Lin, et al.: “A 15.5dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique,” IEEE International Symposium on Circuits and Systems (ISCAS) (2011) 21 (DOI: 10.1109/iscas.2011.5937491).

3. [3] Y. Lim, et al.: “11.5A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers,” ISSCC Dig. Tech. Papers (2014) 202 (DOI: 10.1109/ISSCC.2014.6757400).

4. [4] C. Lee, et al.: “A replica-driving technique for high performance SC circuits and pipelined ADC design,” IEEE Trans. Circuits Syst. II, Exp. Briefs 60 (2013) 557 (DOI: 10.1109/TCSII.2013.2268432).

5. [5] M.S. Akter, et al.: “A capacitively degenerated 100-dB linear 20-150MS/s dynamic amplifier,” IEEE J. Solid-State Circuits 53 (2018) 1115 (DOI: 10.1109/jssc.2017.2778277).

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