A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors-Reference-Cited by-同舟云学术

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A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

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Container-title:IEEE International Electron Devices Meeting 2003
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Author:

Ghani T.,Armstrong M.,Auth C.,Bost M.,Charvat P.,Glass G.,Hoffmann T.,Johnson K.,Kenyon C.,Klaus J.,McIntyre B.,Mistry K.,Murthy A.,Sandford J.,Silberstein M.,Sivakumar S.,Smith P.,Zawadzki K.,Thompson S.,Bohr M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8960/28396/01269442.pdf?arnumber=1269442

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