Development of Epitaxial SiGeB as a Test Vehicle to Evaluate Source-Drain Etchout During Channel Release of Gate-all-Around Devices: Topic/category: AEPM: Advanced Equipment Processes and Materials
Author:
Affiliation:
1. IBM Research,Albany,NY,12203
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10545359/10545360/10545471.pdf?arnumber=10545471
Reference6 articles.
1. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
2. Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
3. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
4. Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors
5. Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors
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