A Test Integration Methodology for 3D Integrated Circuits-Reference-Cited by-同舟云学术

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A Test Integration Methodology for 3D Integrated Circuits

Published:2010-12 Issue: Volume: Page:
ISSN:
Container-title:2010 19th IEEE Asian Test Symposium
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Author:

Chou Che-Wei,Li Jin-Fu,Chen Ji-Jan,Kwai Ding-Ming,Chou Yung-Fa,Wu Cheng-Wen

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5689827/5692210/05692276.pdf?arnumber=5692276

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs;ACM Journal on Emerging Technologies in Computing Systems;2022-10-13

2. Testing 3D-SoCs Using 2-D Time-Division Multiplexing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-12

3. Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design;2018 IEEE 27th Asian Test Symposium (ATS);2018-10

4. Identification of Faulty TSV with a Built-In Self-Test Mechanism;2018 IEEE 27th Asian Test Symposium (ATS);2018-10

5. A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs;IEICE Transactions on Information and Systems;2018-08-01

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