Author:
Hirai Satoshi,Yotsuyanagi Hiroyuki,Hashizume Masaki
Cited by
3 articles.
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1. A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
2. Delay Testable Design Using Modified Boundary Scan;Journal of The Japan Institute of Electronics Packaging;2021-11-01
3. Digital Fault Detection Techniques: A Review;Computers and Devices for Communication;2021