Affiliation:
1. Indian Institute of Engineering Science and Technology, Howrah, West Bengal, India
Abstract
Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture.
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
3 articles.
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1. Storage and Counter Based Logic Built-In Self-Test;IEEE Access;2023
2. Design of Hybrid Memory Built in Self Test using Linear Feedback Shift Registers;2022 6th International Conference on Electronics, Communication and Aerospace Technology;2022-12-01
3. Implementation of Power Binning-based Logic BIST Control using Activity Factor;2022 International Conference on Augmented Intelligence and Sustainable Systems (ICAISS);2022-11-24