Integrated Thermal Management Strategies for 3D Chip Stacking with Through-Silicon Vias (TSV)
Author:
Affiliation:
1. University of Québec in Outaouais,Department of Engineering and Computer Science,Gatineau,QC,Canada,J8X 3X7
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10548014/10548010/10548169.pdf?arnumber=10548169
Reference13 articles.
1. Challenges and recent prospectives of 3D heterogeneous integration
2. Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors
3. Heat transfer enhancement for 3D chip thermal simulation and prediction
4. Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs
5. Compact Thermal Modeling of Emerging Cooling Technologies for Processors
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1. Embedded heat dissipation structure composed of TSVs gradually shrinking from bottom to top in stacked power chips;IEICE Electronics Express;2024
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