Embedded heat dissipation structure composed of TSVs gradually shrinking from bottom to top in stacked power chips
Author:
Affiliation:
1. Department of Electronics Science, Guizhou University
2. Semiconductor Power Device Reliability Engineering Research Center of Ministry of Education
3. Guizhou Provincial Key Lab for Micro-Nano-Electronics and Software
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_21.20240442/_pdf
Reference30 articles.
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3. [3] Y. Satomi, K. Hachiya, T. Kanamoto, R. Watanabe, A. Kurokawa, "Thermal placement on PCB of components including 3D ICs," IEICE Electronics Express, 2020, 17(3), pp. 1-6, doi: 10.1587/elex.17.20190737.
4. [4] G. Chen, R. Sundaram, A. Sekiguchi, K. Hata, and D. N. Futaba, "Through-Silicon-Via Interposers with Cu-Level Electrical Conductivity and Si-Level Thermal Expansion Based on Carbon Nanotube-Cu Composites for Microelectronic Packaging Applications," ACS Appl Nano Mater. 2021, 4(1), pp.869-876, doi:10.1021/acsanm.0c03278.
5. [5] X. Wei, T. Chen and J. Fan, "Low-Temperature Sandwich Structure Wafer-Level Hermetic Packaging via Three-Layer Simultaneous Bonding for 3-D Microsystems," IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(9), pp. 1591-1596, doi: 10.1109/TCPMT.2022.3205336.
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