Thermal placement on PCB of components including 3D ICs-Reference-Cited by-同舟云学术

Thermal placement on PCB of components including 3D ICs

Published:2020 Issue:3 Volume:17 Page:20190737-20190737
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Satomi Yuuta¹,Hachiya Koutaro²,Kanamoto Toshiki¹,Watanabe Ryosuke¹,Kurokawa Atsushi¹

Affiliation:

1. Graduate School of Science and Technology, Hirosaki University

2. Graduate Program in Environmental Information Science, Teikyo Heisei University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/3/17_17.20190737/_pdf

Reference37 articles.

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3. [3] W.-L. Hung, et al.: “Thermal-aware floorplanning using genetic algorithms,” Proc. ISQED (2005) 634 (DOI: 10.1109/ISQED.2005.122).

4. [4] Y. Han and I. Koren: “Simulated annealing based temperature aware floorplanning,” J. Low Power Electron. 3 (2007) 141 (DOI: 10.1166/jolpe.2007.128).

5. [5] S. Logan and M. R. Guthaus: “Fast thermal-aware floorplanning using white-space optimization,” Proc. VLSI-SoC (2009) 65 (DOI: 10.1109/VLSISOC.2009.6041332).

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