Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs-Reference-Cited by-同舟云学术

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Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs

Published:2024-07 Issue:7 Volume:43 Page:1944-1956
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Kim Suwan¹,Park Heechun²^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

2. School of Electrical Engineering, Kookmin University, Seoul, South Korea

Funder

National Research Foundation of Korea

Korea Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/43/10564796/10413507.pdf?arnumber=10413507

Reference32 articles.

1. The 3-D Interconnect Technology Landscape

2. Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices

3. Monolithic 3-D integrated circuits;Wong

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Integrated Thermal Management Strategies for 3D Chip Stacking with Through-Silicon Vias (TSV);2024 4th International Conference on Innovative Research in Applied Science, Engineering and Technology (IRASET);2024-05-16

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