BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell
Author:
Affiliation:
1. Kyushu Institute of Technology,Iizuka,Japan,820-8502
2. Anhui University of Science and Technology,Huainan,China,232001
3. Anhui University,Hefei,China,230000
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10173930/10173940/10174154.pdf?arnumber=10174154
Reference21 articles.
1. A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond
2. Analysis and design of soft-error hardened latches
3. The impact of production defects on the soft-error tolerance of hardened latches
4. High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology
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