Triple-node-upset self-recoverable latch design for aerospace applications
Author:
Funder
National Natural Science Foundation of China
Publisher
Elsevier BV
Reference21 articles.
1. A robust hardened latch featuring tolerance to double-node-upset in 28nm CMOS for spaceborne application;Li;IEEE Trans. Circuits Syst. II,2020
2. LEAP: layout design through fault-aware transistor positioning for soft-fault resilient sequential cell design;Lee;2010 IEEE Int. Reliab. Phys. Symp.,2010
3. Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule;Ibe;IEEE Trans. Electron Devices,2010
4. Low-overhead triple-node-upset-tolerant latch design in 28-nm CMOS;Chen;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2023
5. High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology;Li;Microelectron. Reliab.,2019
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