Design and Performance Analysis of 3-Fin 08 nm Physical Gate Length SOI FinFETs Employing Gate Stacked High-K Dielectrics
Author:
Affiliation:
1. National Institute of Technology,Department of Electronics and Communication Engineering,Aizawl,Mizoram,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10389813/10389825/10390364.pdf?arnumber=10390364
Reference13 articles.
1. Mobility extraction in SOI MOSFETs with sub 1nm body thickness
2. From 2D-planar to 3D-non-planar device architecture: A scalable path forward?
3. Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs
4. It's Time to Redefine Moore's Law Again
5. FinFET: A Beginning of Non-planar Transistor Era
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