Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors-Reference-Cited by-同舟云学术

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Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

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Container-title:2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
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Author:

Ghani T.,Mistry K.,Packan P.,Thompson S.,Stettler M.,Tyagi S.,Bohr M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6881/18528/00852814.pdf?arnumber=852814

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