35 nm CMOS FinFETs-Reference-Cited by-同舟云学术

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35 nm CMOS FinFETs

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Container-title:2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
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Author:

Fu-Liang Yang ,Haur-Ywh Chen ,Fang-Cheng Chen ,Yi-Lin Chan ,Kuo-Nan Yang ,Chih-Jian Chen ,Hun-Jan Tao ,Yang-Kyu Choi ,Mong-Song Liang ,Chenming Hu

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7925/21853/01015409.pdf?arnumber=1015409

Cited by 37 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Physics and Electrical Diagnostics of Nanoelectronic Silicon-On-Insulator Structures and Devices;2023

2. Analysis of Current Fluctuation Due to Trap and Percolation Path in Nano-Scale Bulk FinFET;Journal of Nanoscience and Nanotechnology;2016-05-01

3. Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories;Japanese Journal of Applied Physics;2015-02-26

4. (Invited) Charge Trapping Type SOI-FinFET Flash Memory;ECS Transactions;2014-03-24

5. Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates;Japanese Journal of Applied Physics;2014-01-01

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