Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding-Reference-Cited by-同舟云学术

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Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Published:2007-12 Issue:12 Volume:54 Page:2696-2705
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Vasudevan Dilip P.,Lala Parag K.,Parkerson James Patrick

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/4392469/04378222.pdf?arnumber=4378222

Cited by 41 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and analysis of a novel fast adder using logical effort method;IET Computers & Digital Techniques;2023-07

2. A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology;2023-05-05

3. Design of High-Performance Carry Select Adder using Multiplexer based Logic in 90nm Technology;2023 4th International Conference on Signal Processing and Communication (ICSPC);2023-03-23

4. A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing;ACM Journal on Emerging Technologies in Computing Systems;2022-12-09

5. Optimized Fault-Tolerant Adder Design Using Error Analysis;Journal of Circuits, Systems and Computers;2022-10-25

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