An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology

Abstract

Abstract Conventional carry select adders (CCSA) have two stages and are followed by multiplexers. CCSAs use ripple carry adders at two stages, which will introduce much delay due to carry propagation. To choose the option between an excess-1 result and a normal result, the CCSA employs a multiplexer. The proposed single-stage carry select adder (SSCSA) has a single stage and uses a new block to generate a normal and excess-1 result based on the readily available inputs (A and B). A novel architecture is developed and specifically designed to improve power dissipation and latency. It relies on a single circuit that produces normal/excess-1 results dependent on input carry. Heterogeneous logic combining CMOS, Dual Value Logic, and Transmission Gate Logic with 22 nm Fin-FETs powers the 1-bit SSCSA circuit. Better circuit regularity is displayed by the 4-bit SSCSA, as it only uses one type of 1-bit SSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22 nm FinFET technology, all adders, including 4- and 8-bit adders, are designed, simulated, and examined. According to the resulting study, the 4-bit SSCSA outperforms the best adder among existing adders in terms of speed performance and power dissipation by 17.6% and 27.6%, respectively. By comparison with all other designs, SSCSAs outperform them at every corner.