Design of High-Performance Carry Select Adder using Multiplexer based Logic in 90nm Technology
Author:
Affiliation:
1. Karunya Institute of Technology and Sciences,Coimbatore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10125570/10125282/10125601.pdf?arnumber=10125601
Reference22 articles.
1. An area efficient 64-bit square root carry-select adder for low power application;he;IEEE Int Symp Circuits and Systems (2005),0
2. 64-bit carry-select adder with reduced area
3. A low power and reduced area carry select adder
4. Area and power efficient carry-select adder
5. Performance Analysis of Array Multiplier using low power 10T Full Adder;shylu sam;Proceedings of the Second International Conference on SCI,2018
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1. Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers;National Academy Science Letters;2023-11-22
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