Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers

Author:

Shylu Sam D. S.ORCID,Sam Paul P.,Enoch Mani Deepak B.,Shirley Eva Paul B.,Jayanth B.,Pavitra Kumar K.

Publisher

Springer Science and Business Media LLC

Subject

Engineering (miscellaneous)

Reference29 articles.

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2. Ebrahimi SA, Reshadinezhad MR, Bohlooli A, Shahsavar M (2016) Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits, University of Lille, LIFL, CNRS, UMR 8022. Microelectron J 053:156–166

3. Dhole S, Shembalka S, Yadav T, Thakre P (2017) Design and FPGA implementation of 4x4 vedic multiplier using different architectures. Int J Eng Res Technol 2278–0181

4. Ramkumar Raja M, Ragavi R, Sasisneha S, Ponraj S, Vimalraj P (2018) Comparison between array multiplier and Vedic multiplier. In: International journal of recent trends in engineering & research conference on electronics, information and communication systems, pp 2455–1457

5. Jaya E, Rao K (2016) Power, area and delay comparision of different multipliers. Int J Sci Eng Technol Res 5(6):2093–2100

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