A 115.7–139.7 GHz Amplifier with 19.7 dB Peak Gain and 7.9 dB NF in 40-nm CMOS
Author:
Affiliation:
1. Pohang University of Science and Technology,Department of Electrical Engineering,South Korea
Funder
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10187888/10187785/10187943.pdf?arnumber=10187943
Reference12 articles.
1. Analysis and Design of Dual-Peak Gmax-Core CMOS Amplifier in D-Band Embedding a T-Shaped Network
2. 30 GHz CMOS Low Noise Amplifier
3. A $D$ -Band CMOS Amplifier With a New Dual-Frequency Interstage Matching Technique
4. A 110–125 GHz 27.5 dB Gain Low-power I/Q Receiver Front-end in 65 nm CMOS Technology
5. A 125.5-157 GHz 8 dB NF and 16 dB of Gain D-band Low Noise Amplifier in CMOS SOI 45 nm
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1. A High-Gain D-Band LNA with Compact Gm-Boosting Core Based on Slow-Wave Feedback Achieving 6.1 dB NF in 40 nm CMOS;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16
2. A 70-to-110 GHz 28-nm CMOS Low Noise Amplifier with 6.1-dB NF Minimum Using Differential Noise Optimization;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. Analyze the Loss Utilization in Near- fmax Embedded Amplifiers Using Uniform 3-D Gain Space: The Super-Gain-Boosting Technique;IEEE Transactions on Microwave Theory and Techniques;2024-05
4. D-Band Low-Noise Differential Amplifier in a 40-nm CMOS;The Journal of Korean Institute of Electromagnetic Engineering and Science;2024-04
5. On-Wafer 3rd-Order Intermodulation Distortion Measurement of a D-Band Circuit;The Journal of Korean Institute of Electromagnetic Engineering and Science;2024-04
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