A 110–125 GHz 27.5 dB Gain Low-power I/Q Receiver Front-end in 65 nm CMOS Technology
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8417183/8439129/08439204.pdf?arnumber=8439204
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 131.5–137.5 GHz Low-Power Sub-Harmonic Receiver Using a 65-nm CMOS Technology;IEEE Access;2024
2. A 16.5 mW 4.0 GHz Bandwidth VGA Based on Capacitance Neutralization Technique in 65 nm CMOS;2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2023-10-27
3. Wideband 120-GHz CMOS I/Q Transmitter With Suppressed IMRR and LOFT for Wireless Short-Range High-Speed 6G IoT Applications;IEEE Internet of Things Journal;2023-07-01
4. A 115.7–139.7 GHz Amplifier with 19.7 dB Peak Gain and 7.9 dB NF in 40-nm CMOS;2023 IEEE/MTT-S International Microwave Symposium - IMS 2023;2023-06-11
5. A Review of Integrated Systems and Components for 6G Wireless Communication in the D-Band;Proceedings of the IEEE;2023-03
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