An optimal hardware implementation of the KECCAK hash function on virtex-5 FPGA-Reference-Cited by-同舟云学术

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An optimal hardware implementation of the KECCAK hash function on virtex-5 FPGA

Published:2019-12 Issue: Volume: Page:
ISSN:
Container-title:2019 International Conference on Systems of Collaboration Big Data, Internet of Things & Security (SysCoBIoTS)
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Author:

Assad F.,Elotmani F.,Fettach M.,Tragha A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9022688/9028008/09028020.pdf?arnumber=9028020

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor;International Journal of Parallel Programming;2024-08-29

2. Comparative Study of Keccak SHA-3 Implementations;Cryptography;2023-11-20

3. A Novel Hardware Architecture for Enhancing the Keccak Hash Function in FPGA Devices;Information;2023-08-28

4. High-Speed Hardware Architecture Based on Error Detection for KECCAK;Micromachines;2023-05-27

5. A High-Performance Pipelined FPGA-SoC Implementation of SHA3-512 for Single and Multiple Message Blocks;Intelligence of Things: Technologies and Applications;2023

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