Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

Author:

Sanlı MustafaORCID

Publisher

Springer Science and Business Media LLC

Reference19 articles.

1. Bertoni, G., Daemen, J., Peeters, M., Van Assche, G.: Keccak sponge function family main document. NIST 30, 320 (2009)

2. NIST-FIPS 180–3, Secure Hash Standard (SHS), NIST (2008).

3. Kahri, F., Mestiri, H., Bouallegue, B., Machhout, M.: Fault attacks resistant architecture for Keccak hash function. Int. J. Adv. Comput. Sci. Appl. 8(5), 237–243 (2017)

4. Sideris A, Sanida T Dasygenis M (2022) High throughput pipelined implementation of the SHA-3 cryptoprocessor. In: 32nd International Conference on Microelectronics (ICM), pp. 1–4

5. Homsirikamol E, Rogawski M, Gaj K (2010) Comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs. Cryptology ePrint Archive Report, George Mason University

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