Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs-Reference-Cited by-同舟云学术

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Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs

Published:2010-01 Issue: Volume: Page:
ISSN:
Container-title:2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
language:
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Author:

Zhao Xin,Lim Sung Kyu

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5415928/5419673/05419900.pdf?arnumber=5419900

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Hierarchical Clock Network Synthesis Method for 3D Integrated Circuits with Obstacle Avoidance;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

2. An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC;IET Computers & Digital Techniques;2018-11-27

3. Power Efficient 3D Clock Distribution Network Design with TSV Count Optimization;Procedia Computer Science;2016

4. Low Power Clock Routing for 3D IC;Design for High Performance, Low Power, and Reliable 3D Integrated Circuits;2012-09-24

5. On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs;Journal of Electronic Testing;2011-11-03

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