On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs

Published:2011-11-03 Issue:1 Volume:28 Page:93-101
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Buttrick Michael,Kundu Sandip

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s10836-011-5262-3.pdf

Reference11 articles.

1. Arora M (2002) Clock dividers made easy. Design flow & reuse. ST Microelectronics Ltd, SNUG, Boston

2. Beck M et al (2005) Logic design for on-chip test clock generation- implementation details and impact on delay test quality. in DATE

3. Farjad-Rad R et al (2002) A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J Solid State Circ 37(12):1804–1812

4. Friedman E (2001) Clock distribution networks in synchronous digital integrated circuits. Proc IEEE 89(5):665–692

5. Marinissen EJ, Zorian Y (2009) Testing 3D chips containing through-silicon vias. in International test conference.

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Repairing a 3-D Die-Stack Using Available Programmable Logic;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2015-05

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP