A world's first product of three-dimensional vertical NAND Flash memory and beyond
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7054077/7060833/07060840.pdf?arnumber=7060840
Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE);IEEE Transactions on Electron Devices;2024-03
2. Necking Reduction at Low Temperature in Aspect Ratio Etching of SiO2 at CF4/H2/Ar Plasma;Nanomaterials;2024-01-17
3. Fundamental Issues in VNAND Integration Toward More Than 1K Layers;2023 International Electron Devices Meeting (IEDM);2023-12-09
4. Voltage scheme for string-select transistors to improve inhibition characteristics during 1-bit erase in vertical NAND flash;Applied Physics Letters;2023-10-02
5. Neural Network Based Threshold Voltage Model for 3D TLC NAND Flash;2023 IEEE 16th International Conference on Electronic Measurement & Instruments (ICEMI);2023-08-09
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