Quantized Neural Network Synthesis for Direct Logic Circuit Implementation-Reference-Cited by-同舟云学术

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Quantized Neural Network Synthesis for Direct Logic Circuit Implementation

Published:2023-02 Issue:2 Volume:42 Page:473-482
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Huang Yu-Shan¹^ORCID,Jiang Jie-Hong R.²^ORCID,Mishchenko Alan³

Affiliation:

1. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

2. Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

3. Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA

Funder

Ministry of Science and Technology of Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/10021949/09796650.pdf?arnumber=9796650

Reference29 articles.

1. Laconic deep learning inference acceleration

2. Logic synthesis of binarized neural networks for efficient circuit implementation

3. Resource-optimized combinational binary neural network circuits

4. Energy-efficient, low-latency realization of neural networks through boolean logic minimization

5. Unrolling Ternary Neural Networks

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