Energy-efficient, low-latency realization of neural networks through boolean logic minimization-Reference-Cited by-同舟云学术

Energy-efficient, low-latency realization of neural networks through boolean logic minimization

Published:2019-01-21 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 24th Asia and South Pacific Design Automation Conference
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Author:

Nazemi Mahdi¹,Pasandi Ghasem¹,Pedram Massoud¹

Affiliation:

1. University of Southern California

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3287624.3287722

Reference19 articles.

1. M. Nazemi G. Pasandi and M. Pedram. NullaNet: Training deep neural networks for reduced-memory-access inference. arXiv preprint arXiv:1807.08716 2018. M. Nazemi G. Pasandi and M. Pedram. NullaNet: Training deep neural networks for reduced-memory-access inference. arXiv preprint arXiv:1807.08716 2018.

2. Intel 64 and IA-32 architectures optimization reference manual. https://software.intel.com. Intel 64 and IA-32 architectures optimization reference manual. https://software.intel.com.

3. Intel Haswell. https://www.7-cpu.com/cpu/Haswell.html. Intel Haswell. https://www.7-cpu.com/cpu/Haswell.html.

4. 1.1 Computing's energy problem (and what we can do about it)

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