PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
Author:
Affiliation:
1. Imperial College London,Department of Electrical and Electronic Engineering,UK
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10415908/10416087/10416099.pdf?arnumber=10416099
Reference20 articles.
1. Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review
2. Deep Neural Network Approximation for Custom Hardware
3. LUTNet: Rethinking Inference in FPGA Soft Logic
4. LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
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1. FPGA Acceleration of Dynamic Neural Networks: Challenges and Advancements;2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS);2024-07-29
2. Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04
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