HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS-Reference-Cited by-同舟云学术

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS

Published:2023-11 Issue:11 Volume:42 Page:3925-3938
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Lin Zhe¹^ORCID,Liang Tingyuan²^ORCID,Zhao Jieru³^ORCID,Sinha Sharad⁴^ORCID,Zhang Wei²^ORCID

Affiliation:

1. School of Integrated Circuits, Sun Yat-sen University, Shenzhen, China

2. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, China

3. Department of Computer Science and Engineering, Shanghai Jiaotong University, Shanghai, China

4. Department of Computer Science and Engineering, Indian Institute of Technology Goa, Goa, India

Funder

the Major Key Project of PCL

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference46 articles.

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1. Power Analysis;FPGA EDA;2024

2. Design Scalability and Power Optimization of Power Management Unit;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02