Author:
Wang Yuxin,Li Peng,Zhang Peng,Zhang Chen,Cong Jason
Cited by
36 articles.
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1. HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1;2024-04-17
2. Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
3. HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
4. Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
5. Optimizing Data Reuse for CGRA Mapping Using Polyhedral-based Loop Transformations;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09