LegUp

Author:

Canis Andrew1,Choi Jongsok1,Aldham Mark1,Zhang Victor1,Kammoona Ahmed1,Czajkowski Tomasz2,Brown Stephen D.1,Anderson Jason H.1

Affiliation:

1. University of Toronto, ON, Canada

2. Altera Corporation, ON, Canada

Abstract

It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this article, we introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixed-sized multidimensional arrays, structs, global variables, and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software codesign space by varying the amount of a program that runs in software versus hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of high-level synthesis topics.

Funder

Natural Sciences and Engineering Research Council of Canada

Natural Sciences and Engineering Research Council (NSERC) of Canada and Altera Corporation

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Reference44 articles.

1. Low-cost hardware profiling of run-time and energy in FPGA embedded processors

2. Altera Corp. 2009. Nios II C2H Compiler User Guide. Altera Corp. San Jose CA. Altera Corp. 2009. Nios II C2H Compiler User Guide. Altera Corp. San Jose CA.

3. Altera Corp. 2010. Avalon interface specification. Altera Corp. San Jose CA. Altera Corp. 2010. Avalon interface specification. Altera Corp. San Jose CA.

4. Altera Corp. 2011. Stratix IV FPGA family data sheet. Altera Corp. San Jose CA. Altera Corp. 2011. Stratix IV FPGA family data sheet. Altera Corp. San Jose CA.

5. AutoESL. 2011. AutoESL Design Technologies Inc. http://www.autoesl.com. AutoESL. 2011. AutoESL Design Technologies Inc. http://www.autoesl.com.

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