Wavefront Threading Enables Effective High-Level Synthesis

Author:

Pelton Blake1ORCID,Sapek Adam1ORCID,Eguro Ken1ORCID,Lo Daniel1ORCID,Forin Alessandro1ORCID,Humphrey Matt1ORCID,Xi Jinwen1ORCID,Cox David1ORCID,Karandikar Rajas1ORCID,de Fine Licht Johannes2ORCID,Babin Evgeny1ORCID,Caulfield Adrian1ORCID,Burger Doug1ORCID

Affiliation:

1. Microsoft, Redmond, USA

2. ETH Zurich, Zurich, Switzerland

Abstract

Digital systems are growing in importance and computing hardware is growing more heterogeneous. Hardware design, however, remains laborious and expensive, in part due to the limitations of conventional hardware description languages (HDLs) like VHDL and Verilog. A longstanding research goal has been programming hardware like software, with high-level languages that can generate efficient hardware designs. This paper describes Kanagawa, a language that takes a new approach to combine the programmer productivity benefits of traditional High-Level Synthesis (HLS) approaches with the expressibility and hardware efficiency of Register-Transfer Level (RTL) design. The language's concise syntax, matched with a hardware design-friendly execution model, permits a relatively simple toolchain to map high-level code into efficient hardware implementations.

Publisher

Association for Computing Machinery (ACM)

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