Reliability and PVT simulation of FinFET circuits using Cadence Virtuoso-Reference-Cited by-同舟云学术

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Reliability and PVT simulation of FinFET circuits using Cadence Virtuoso

Published:2021-12-10 Issue: Volume: Page:
ISSN:
Container-title:2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT)
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Author:

Kajal ¹,Sharma Vijay Kumar¹

Affiliation:

1. Shri Mata Vaishno Devi University,School of Electronics and communication Engineering,Katra,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9707901/9707891/09707937.pdf?arnumber=9707937

Reference19 articles.

1. Performance estimation of junctionless multigate transistors

2. FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

3. Impact of different transistor arrangements on gate variability

4. Ultrafast Measurements and Physical Modeling of NBTI Stress and Recovery in RMG FinFETs Under Diverse DC–AC Experimental Conditions

5. Study on device reliability for P-type FinFETs with different fin numbers

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime;Current Nanoscience;2024-05

2. Review of the Nanoscale FinFET Device for the Applications in Nano-regime;Current Nanoscience;2023-09

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