Optimizing 20V LDNMOS Transistors for PMIC Applications by Simulation Tools
Author:
Affiliation:
1. Vanguard International Semiconductor Corporation,Hsinchu,Taiwan
2. National Tsing-Hua University,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9868970/9868972/09869035.pdf?arnumber=9869035
Reference5 articles.
1. A novel LDMOS structure with a step gate oxide
2. Characterization and modeling of electrical stress degradation in STI-based integrated power devices
3. Planar dual gate oxide LDMOS structures in 180nm power management technology
4. A new lateral power MOSFET for smart power ICs: the “LUDMOS concept”
5. Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor With Multiple Floating Poly-Gate Field Plates
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