Planar dual gate oxide LDMOS structures in 180nm power management technology-Reference-Cited by-同舟云学术

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Planar dual gate oxide LDMOS structures in 180nm power management technology

Published:2012-06 Issue: Volume: Page:
ISSN:
Container-title:2012 24th International Symposium on Power Semiconductor Devices and ICs
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Author:

Sharma Santosh,Letavic Theodore,Shi Yun,Loiseau Alain,Monaghan John-Ellis,Feilchenfeld Natalie,Phelps Rick,Lamothe Christopher,Cook Don,Dunn Jim,Roerher Georg,Nauschnig Helmut,Minixhofer Rainer

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6222389/6228999/06229107.pdf?arnumber=6229107

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Substrate Current Improvement and Investigation in Low Voltage Power Ldmos with A Novel Design;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

2. Optimizing 20V LDNMOS Transistors for PMIC Applications by Simulation Tools;2022 IEEE International Conference on Consumer Electronics - Taiwan;2022-07-06

3. Study on 20 V LDMOS With Stepped-Gate-Oxide Structure for PMIC Applications: Design, Fabrication, and Characterization;IEEE Transactions on Electron Devices;2022-02

4. New Strained LDMOS With Ultralow ON-Resistance by Si1−y C y Source Stressor for About 20 V Low-Voltage Applications;IEEE Transactions on Electron Devices;2020-11

5. Investigation and Demonstration of Hot Carrier Effect in LDMOS Transistors with Ultra-Shallow Trench Isolation;2020 China Semiconductor Technology International Conference (CSTIC);2020-06-26

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