Study on 20 V LDMOS With Stepped-Gate-Oxide Structure for PMIC Applications: Design, Fabrication, and Characterization
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9690079/09648223.pdf?arnumber=9648223
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications;Transactions on Electrical and Electronic Materials;2024-04-04
2. Determining the Performance Limits of LDMOS With Three Common Types of Field Oxides;IEEE Transactions on Electron Devices;2024-04
3. Dual‐Stepped Gate Vertical Double‐Diffused Metal‐Oxide‐Semiconductor Field‐Effect Transistor with Enhanced Device Performance;physica status solidi (a);2024-01-23
4. Experiments of a Novel Low-Voltage LDMOS With Ultrashallow Low-Resistance Path Modulated by Bulk Superjunction;IEEE Transactions on Electron Devices;2024-01
5. A Physics-Based Compact Model for the Static Drain Current in Heterojunction Barrier CNTFETs—Part II: Scattering, High-Field Effects, and Model Verification;IEEE Transactions on Electron Devices;2024-01
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