Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices-Reference-Cited by-同舟云学术

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Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices

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Container-title:2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)
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Author:

Bansal A.,Paul B.C.,Roy K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/9580/30296/01391570.pdf?arnumber=1391570

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