Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
http://link.springer.com/content/pdf/10.1007/s12633-020-00424-2.pdf
Reference44 articles.
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3. Singh R, Aditya K, Parihar SS, Chauhan YS, Vega R, Hook TB, Dixit A (2018) Evaluation of 10-nm Bulk finFET RF performance—conventional versus NC-finFET. Electron Devices Letter 36(8):1246–1249. https://doi.org/10.1109/LED.2018.2846
4. Datta A, Goel A, Cakici RT, Mahmoodi H, Lekshmanan D, Roy K (2007) Modeling and circuit synthesis for independently controlled double gate finFET devices. IEEE Trans Electron Devices 26(11):1957–1966. https://doi.org/10.1109/TCAD.2007.896320
5. Cakici T, Mahmoodi H, Mukhopadhyay S, Roy K (2005) Independent gate skewed logic in double gate SOI technology. In: Proc IEEE Int SOI Conf, pp 83–84. https://doi.org/10.1109/SOI.2005.1563543
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