Physical insights on design and modeling of nanoscale FinFETs-Reference-Cited by-同舟云学术

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Physical insights on design and modeling of nanoscale FinFETs

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Container-title:IEEE International Electron Devices Meeting 2003
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Author:

Fossum J.G.,Chowdhury M.M.,Trivedi V.P.,King T.-J.,Choi Y.-K.,An J.,Yu B.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8960/28396/01269371.pdf?arnumber=1269371

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study of Nanosheet Performance by Varying the Aspect Ratio;2023 World Conference on Communication & Computing (WCONF);2023-07-14

2. Ultra-low-power subthreshold logic with germanium junctionless transistors;Semiconductor Science and Technology;2021-06-08

3. Improvising the Switching Ratio through Low-k / High-k Spacer and Dielectric Gate Stack in 3D FinFET - a Simulation Perspective;Silicon;2020-08-03

4. Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application;Silicon;2020-03-13

5. Impact of Sidewall Spacer Layers on the Analog/RF Performance of Nanoscale Double-Gate Junctionless Transistors;Proceedings of the International Conference on Microelectronics, Computing & Communication Systems;2017-12-30

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