Highly Stacked GeSn Nanosheets by CVD Epitaxy and Highly Selective Isotropic Dry Etching

Author:

Huang Bo-Wei1ORCID,Tsai Chung-En1ORCID,Liu Yi-Chun1ORCID,Tu Chien-Te1ORCID,Hsieh Wan-Hsuan1ORCID,Jan Sun-Rong1,Chen Yu-Rui1ORCID,Chueh Shee-Jier1ORCID,Cheng Chun-Yi1ORCID,Liu C. W.2ORCID

Affiliation:

1. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

2. Department of Electrical Engineering, the Graduate Institute of Electronics Engineering, the Graduate Institute of Photonics and Optoelectronics, and the Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan

Funder

Ministry of Science and Technology, Taiwan

Ministry of Education, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference35 articles.

1. High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process

2. First demonstration of high-Ge-content strained-Si1-xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications;hashemi;IEDM Tech Dig,2014

3. Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

4. The First GeSn Gate-All-Around Nanowire P-FET on the GeSnOI Substrate with Channel Length of 20 nm and Subthreshold Swing of 74 mV/decade

5. High-mobility high-Ge-content Si1-xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x~0.7, scaled EOT 8.5Å and 10nm fin width;hashemi;Prop VLSI Technol,2015

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