3-D Modeling of Fringe Gate Capacitance in Complementary FET (CFET)-Reference-Cited by-同舟云学术

3-D Modeling of Fringe Gate Capacitance in Complementary FET (CFET)

Published:2022-11 Issue:11 Volume:69 Page:5978-5984
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Yang Xiaoqiao¹^ORCID,Sun Yabin¹^ORCID,Liu Ziyu²,Liu Yun¹,Li Xiaojin¹^ORCID,Shi Yanling¹

Affiliation:

1. Department of Electrical Engineering, Shanghai Key Laboratory of Multidimensional Information Processing, East China Normal University, Shanghai, China

2. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China

Funder

National Natural Science Foundation of China

Natural Science Foundation of Shanghai

Shanghai Science and Technology Innovation Action Plan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9926983/09912378.pdf?arnumber=9912378

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