Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm
Author:
Affiliation:
1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
Funder
Strategic Priority Research Program of Chinese Academy of Sciences
NSFC
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10328902/10292591.pdf?arnumber=10292591
Reference33 articles.
1. A Machine Learning Approach for Optimization of Channel Geometry and Source/Drain Doping Profile of Stacked Nanosheet Transistors
2. Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond
3. A comprehensive study of device variability of sub-5 nm nanosheet transistors and interplay with quantum confinement variation
4. Transistor Compact Model Based on Multigradient Neural Network and Its Application in SPICE Circuit Simulations for Gate-All-Around Si Cold Source FETs
5. Measurements of bandgap narrowing in Si bipolar transistors
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