Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs
Author:
Affiliation:
1. Department of Electrical Engineering, IIT Kanpur, Kanpur, India
Funder
Indian Institute of Technology Kanpur
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10382412/10148095.pdf?arnumber=10148095
Reference35 articles.
1. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
2. FinFET scaling to 10 nm gate length
3. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
4. Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices
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1. Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break;IEEE Transactions on Electron Devices;2024-07
2. Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance;ECS Journal of Solid State Science and Technology;2024-06-03
3. Parasitic Capacitance in Nanosheet FETs: Extraction of Different Components and Their Analytical Modeling;IEEE Transactions on Electron Devices;2024-05
4. Analytical Model for Parasitic Resistance of N-stack Forksheet FETs Using Modified Transmission Line Method;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03
5. Parasitic Gate Capacitance Model for N-Stack Forksheet FETs;IEEE Transactions on Electron Devices;2024-03
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