Underfill Affect Study on Chip Stress in Board & Set Level Drop Test
Author:
Affiliation:
1. Samsung Semiconductor(China)R&D CO., LTD,Packaging Technology Development Team,Suzhou,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9872527/9872536/09873306.pdf?arnumber=9873306
Reference8 articles.
1. Effect of underfills on board level reliability of area array package with stress calculation
2. Drop performance evaluation for application of different underfill processes
3. Underfill and edgebond for enhancing of board level reliability (IMPACT 2014)
4. Effect of Unfilled Underfills on Drop Impact Reliability Performance of Area Array Packages
5. A novel completely explicit algorithm to solve dynamic u-p equations of saturated soil;xu;Soil Dynamics and Earthquake Engineering,2020
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